Modern power semiconductor devices, such as power MOSFETs, HEMTs, and Insulated Gate Bipolar Transistors (IGBTs), have been typically fabricated with silicon (Si) semiconductor materials. More recently, silicon carbide (SiC) power devices have been developed due to their superior properties. III-N (III-N) semiconductor devices have many potential advantages over silicon and SiC based devices for high power electronics applications, and are now emerging as an attractive candidate to carry large currents, support high voltages, provide very low on resistances, and operate at high voltages with fast switching times.
As large III-N substrates are not yet widely available, III-N semiconductor devices are currently grown by heteroepitaxy on suitable foreign substrates (i.e., substrates that differ substantially in composition and/or lattice structure from that of the deposited layers). Typically, III-N semiconductor devices are grown on silicon, sapphire (Al2O3), or silicon carbide (SiC) substrates. Techniques for applying the III-N layers can include molecular beam epitaxy (MBE), metal organic chemical vapor deposition (MOCVD), and hydride vapor phase epitaxy (HYPE). Silicon substrates are emerging as a particularly attractive substrate candidate for III-N devices due to their low cost, wide availability, large wafer sizes, thermal properties, and ease of integration with silicon-based electronics. Due to the large lattice mismatch and thermal expansion coefficient mismatch between silicon and III-N materials, III-N device structures typically include nucleation and stress management layers to allow for growth of thick III-N layers.
A typical prior art III-N high electron mobility transistor (HEMT), shown in FIG. 1, includes a foreign substrate 10, such as silicon, a nucleation layer 9 atop the substrate, such as AlN or AlxGa1-xN, a stress management stack 8 atop the nucleation layer, such as AlN/GaN or AlxGa1-xN/GaN superlattices, a channel layer 11, such as a layer of GaN atop the stress management stack 8, and a barrier layer 12, such as a layer of AlxGa1-xN, atop the channel layer. A two-dimensional electron gas (2 DEG) channel 19 (illustrated by a dotted line) is induced in the channel layer 11 near the interface between the channel layer 11 and the barrier layer 12. Source and drain electrodes 14 and 15, respectively, which are formed on opposite sides of the gate electrode 16, contact the 2 DEG channel 19 in channel layer 11. Gate 16 modulates the portion of the 2 DEG in the gate region, i.e., directly beneath gate 16. Insulator layer 13, such as a layer of SiN, atop barrier layer 12, is a surface passivation layer that prevents or suppresses voltage fluctuations at the surface of the barrier layer adjacent to insulator layer 13.
The heteroepitaxial growth or deposition of the III-N epitaxial layers of the device on foreign substrate 10 necessitates the inclusion of intermediate layers between the substrate 10 and the channel layer 11, which include nucleation layer 9 and stress management stack 8, in order to minimize the deleterious effects of the thermal and lattice mismatches between III-N device layers and the foreign substrate 10, such as defect formation and stress in the layers. However, these intermediate layers typically have a high concentration of dislocations, trapping centers, and other defects which can be detrimental to device performance. Such defects can trap charge (i.e., have an electric potential that can attract and bind electrons such that the bound electrons do not contribute to the current in the device or result in instabilities such as threshold voltage fluctuations) while a voltage is applied to the device during operation. The nucleation and stress management layers can therefore cause a difference in current-voltage characteristics from those that would be observed if the device did not contain these layers.
It has been found that the removal of nucleation layer 9 and stress management stack 8, which can be accessed and removed after the removal of the underlying foreign substrate 10, can allow for a device having superior device properties that are very important for high-voltage III-N device applications. The removal of these layers can enable a device to operate at high voltage without being subject to substantial trapping, leakage, or early breakdown effects, thereby being superior compared to III-N devices that have not had their native substrates and stress management layers removed.